Examples of a surface-mount package for a semiconductor chip include BGAs and quad flat packages (QFPs). A BGA is a surface-mount package developed for a large scale integrated circuit (LSI) that has more pins than those in a QFP, which is a flat package that has leads extending in four directions. BGAs are very much used, as semiconductor packages for high-speed devices, in portable machines, such as cellular phones, or personal computers. A BGA package is joined to a mounting board by use of conductive balls (bumps) arranged in an array on its back as external terminals, instead of using a lead frame. Because the entire back surface of the semiconductor package can be used for connection to the board, the number of input/output pads can be markedly increased. However, to support recent higher functionality, the number of pins, i.e., input/output pins is being remarkably increased. One example of a BGA that supports multiple pins is a plastic BGA (PBGA) that uses an organic substrate as an interposer substrate (interposer). Although the bonding method or the number of wiring layers of an interposer may be different, a typical PBGA has a two-layer or multilayer structure, which enables multilayer wiring. Therefore, PBGAs can find wide application.
Although wire bonding is the mainstream of the bonding method, flip chip bonding is used in low resistance connection for high-speed application. For high heat dissipation (radiation) application, a structure that includes a radiating plate (or heatsink) at the surface of a package can also be used. Flip chip bonding using a BGA is effective for improvement in speed and functionality, but it is a relatively expensive packaging technology. With recent advances in circuit technology, attention is given to wire bonding using a BGA, which again achieves high functionality but inexpensive technology.
As illustrated in FIG. 13, a typical BGA semiconductor package 900 generally has a structure in which a ball grid array 920 including solder balls arranged on the back surface of a semiconductor chip 910 is soldered to an interposer substrate 930. The interposer substrate 930 is connected to pads 950 disposed on the upper surface of an external circuit board 960 by use of bumps or solder balls 940.
In design of known BGA packages using boding wires, in order to reduce wiring resistance in a semiconductor chip, wiring in the semiconductor chip is devised. For example, the length of a wire connected to each connection pad on the periphery of the semiconductor chip is minimized, thus reducing electrical resistance; or the number of pads for the ground and the power supply on the semiconductor chip is increased. However, when the chip size increases, the distance from the connection pad at the periphery of the chip to the central portion becomes long and wiring resistance is thus increased. This may lead to a decrease in stability of device operation caused by a voltage drop (IR drop).
A BGA flip-chip connected package in which solder bumps arranged in an array are connected to an interposer substrate is significantly more expensive than a BGA wire-bonded package because, although the effect of reducing a voltage drop at the central portion of the chip is large, it is necessary to form bumps and fine rules for substrate design.
Patent Document 1 discloses a method for establishing electric connections in a semiconductor by use of a second conductor connection portion (for use in supplying power and having a grid structure) bridging an electrode pad adjacent to the central portion of a principal surface of a semiconductor chip (central electrode) and an external terminal to prevent a voltage drop in the semiconductor chip. The electric connections of the grid conductor connection portion are established on the chip and the substrate, and the structure is held only by this electric connection portion. As a result, reliability of the joining portion and stability of holding of the structure may be impaired by a mismatch of thermal expansion coefficients of packaging materials.
Patent Document 2 discloses a semiconductor device that uses two conductive materials different from a normal lead frame for power-supply lines (Vdd, GND) in a semiconductor chip. More specifically, the plane of a conductor includes divided regions such that one corresponds to the power supply and the other corresponds to the ground. A terminal dedicated to input/output signals and a terminal dedicated to the power supply are provided. Because any number of power-supply dedicated leads can be arranged at any location of the chip, this device is advantageous in that the occurrence of malfunction resulting in a voltage drop is reduced. In this package, a pin extending from the conductor attached on the chip is connected to the outside (circuit) above the chip, whereas a signal line is connected from a lead on the periphery of the package. Therefore, the loop inductance of a power supply-signal line path is increased.
Patent Document 3 discloses a method for wire-bonding an electrode exposed on an electrode arrangement surface of a semiconductor chip to a conductive plane (power-supply plane and a ground plane) formed by processing a conductor film on a chip mounting surface of an insulating substrate of a semiconductor package to reduce parasitic inductance caused by the length of a bonding wire. The conductor chip electrode is not present at the central portion of the chip. The conductive plane is a single thin film, and the power-supply lines are divided in a planar manner.
[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-203634
[Patent Document 2] Japanese Unexamined Patent Application Publication No. 10-27863
[Patent Document 3] Japanese Unexamined Patent Application Publication No. 11-204688